The present invention relates to a level shift circuit and an image display device employing the circuit, and in particular, to a level shift circuit that is incorporated in an image display device of a driver monolithic type (drive circuit integrated type) and amplifies an input signal having small amplitude (logic level) and the image display device.
In recent years, researches and developments of display devices employing liquid crystals have been remarkably promoted, and in particular, a TFT (Thin Film Transistor) liquid crystal display device employing polysilicon is expected to have great demands in future. The TFT liquid crystal display device employing polysilicon has electron and hole mobility that is two orders of magnitude greater than that of a device employing amorphous silicon and is able to have a CMOS structure of a combination of an n-channel TFT and a p-channel TFT. Therefore, in contrast to the TFT liquid crystal display device employing amorphous silicon in which the drive circuit must be formed of, for example, single crystal silicon outside the substrate of a pixel TFT for a liquid crystal cell, a drive circuit can be formed on a substrate identical to that of the pixel TFT for the liquid crystal cell using polysilicon. That is, a driver monolithic type TFT liquid crystal display device can be formed, and this allows the compacting, functional improvement and cost reduction to be achieved.
FIG. 11 shows the construction of the driver monolithic type TFT liquid crystal display device. FIG. 11 shows a video signal terminal 1 for inputting a video signal from the outside, a counter voltage terminal 2 for inputting a voltage to an opposite electrode, a shift register 3 for driving n (n: integer n greater than 1) gate bus lines, a shift register 4 for driving m (m: integer m greater than 1) source bus lines, level shift circuits 5 through 8 for amplifying the amplitude of an input control signal, a start pulse SPV to be inputted to the shift register 3, clock signals xcfx861V and xcfx862V having a frequency equal to a horizontal period, drive pulses xcfx86V1 through xcfx86Vn that are to turn on and off TFT elements and outputted from the shift register 3, gate bus lines G1 through Gn, a start pulse SPH to be inputted to the shift register 4, clock signals xcfx861H and xcfx862H having a frequency m times the horizontal period, sampling pulses xcfx86H1 through xcfx86Hm outputted from the shift register 4, sampling switches M1 through Mm to sample a video signal, source bus lines L1 through Lm, TFT elements M11 through Mnm provided at the intersections of the source bus lines L1 through Lm and the gate bus lines G1 through Gn and liquid crystal cells C11 through Cnm that exist between the pixel electrodes and the opposite electrodes connected to the TFT elements M11 through Mnm.
In FIG. 11, the level shift circuits 5 through 8 are provided with a circuit for amplifying the amplitudes of the start pulses SPV and SPH and the clock signals xcfx861V, xcfx862V, xcfx861H and xcfx862H. In the driver monolithic type TFT liquid crystal display device, the drive circuit is constructed of polysilicon. However, the threshold voltage of the transistor becomes higher than that of a device whose drive circuit is formed of single crystal silicon. Therefore, the amplification levels of the start pulses SPV and SPH and the clock signals xcfx861V, xcfx862V, xcfx861H and xcfx862H, which have logic level power voltages of 3 V, 3.3 V and 5 V, are not regarded as sufficiently high. The levels are required to be raised up to a voltage of, for example, 12 to 15 V, for which the level shift circuits 5 through 8 are provided.
FIG. 12 shows a conventional level shift circuit. FIG. 12 shows a positive power voltage VDD, a negative power voltage GND, an input signal IN, an input signal (/IN) whose voltage level is inverted relative to the input signal IN, an output signal OUT, p-channel TFT""s p121, p122 and p123, and n-channel TFT""s n121, n122 and n123.
In FIG. 12, the input signal IN is inputted to the gate of an n-channel TFT n121, while the input signal (/IN) is inputted to the gate of an n-channel TFT n122. The drain of the n-channel TFT n121 is connected to the drain and gate of a p-channel TFT p121 and the gate of a p-channel TFT p122, while the drain of the n-channel TFT n122 is connected to the drain of the p-channel TFT p122 and an input terminal of an inverter circuit section constructed of a p-channel TFT p123 and an n-channel TFT n123. The source of the p-channel TFT p121 and the source of the p-channel TFT p122 are connected to the positive power voltage VDD, while the source of the n-channel TFT n121 and the source of the n-channel TFT n122 are connected to the negative power voltage GND.
Reference is made to the operation of the conventional level shift circuit shown in FIG. 12. If the input signal IN has high level and the input signal (IN) has low level, then the n-channel TFT n121 is turned on, and the n-channel TFT n122 is turned off. Then, the negative power voltage GND is inputted to the gate of the p-channel TFT p121 and the gate of the p-channel TFT p122, when the p-channel TFT p121 is regarded as a resistance component, flowing a current between the positive power voltage VDD and the negative power voltage GND. On the other hand, the p-channel TFT p122 is turned on, by which the drain of the p-channel TFT p122 and the input terminal of the inverter circuit section constructed of the p-channel TFT p123 and the n-channel TFT n123 are charged with the positive power voltage VDD, outputting the negative power voltage GND from the output terminal of the inverter circuit section. If the input signal IN is inverted to low level and the input signal (/IN) is inverted to high level, then the n-channel TFT n121 is turned off, and the n-channel TFT n122 is turned on. Then, the input terminal of the inverter circuit section constructed of the p-channel TFT p123 and the n-channel TFT n123 is discharged to the negative power voltage GND, and the positive power voltage VDD is outputted from the output terminal of the inverter circuit section. That is, the amplitude of the input is signal IN is amplified by the conventional level shift circuit shown in FIG. 12. (It is to be noted that a potential difference between the positive power voltage VDD and the negative power voltage GND is set higher than the amplitude of the input signal IN).
If the conventional level shift circuit shown in FIG. 12 is constructed of polysilicon similarly to the other drive circuit, then the threshold voltage of each transistor becomes higher than the voltage formed by single crystal silicon. During the processes of forming transistors, it is sometimes the case where variation in threshold voltage increases. The rise in transistor threshold voltage leads to an increase in transistor ON-state resistance. If the ON-state resistances of the p-channel TFT""s p121 and p122 and the n-channel TFT""s n121 and n122 become high, then a time constant of charging and discharging the input terminal of the inverter circuit section constructed of the p-channel TFT p123 and the n-channel TFT n123 is increased. In contrast to this, the amplitudes of the start pulses SPV and SPH and the clock signals xcfx861V, xcfx862V, xcfx861H and xcfx862H, which have logic level power voltages of 3 V, 3.3 V and 5 V, are not regarded as sufficiently high. This has led to the problem that the waveform of an output from the level shift circuit has become dull or distorted.
In view of the above, it can be considered to increase the transistor channel width in order to reduce the time constant. However, if the transistor channel width is increased, then this leads to the increase in area of the level shift circuit. Furthermore, if the transistor channel width is increased, then the capacity of the transistor itself concurrently increases. Therefore, even if the transistor channel width is increased, then the effect of reducing the time constant is not proportional to the size of the transistor channel width.
As a technique for solving the above-mentioned problem, for example, Japanese Patent Laid-Open Publication No. HEI 4-242317 and the like are proposed. FIG. 13 shows the conventional level shift circuit disclosed in this Japanese Patent Laid-Open Publication No. HEI 4-242317. FIG. 13 shows a positive power voltage VB, resistors R131 and R132, capacitors C131 and C132, npn-type bipolar transistors T131, and T132, p-channel TFT""s p131, p132 and p133, n-channel TFT""s n131, n132 and n133 and other components similar to those of FIG. 12.
FIG. 13 is constituted by a voltage clamp circuit section constructed of the positive power voltage VB, negative power voltage GND, resistors R131 and R132 and npn-type bipolar transistors T131 and T132, and a level shift circuit section constructed of the positive power voltage VDD, negative power voltage GND, p-channel TFT""s p131, p132 and p133 and n-channel TFT""s n131, n132 and n133. In the voltage clamp circuit section, a voltage obtained by dividing the voltage across the positive power voltage VB and the negative power voltage GND by the resistors R131 and R132 (this voltage defined as a voltage VBxe2x80x2) is inputted to the base of the npn-type bipolar transistor T131 and the base of the transistor T132. The emitter of the npn-type bipolar transistor T132 is connected to one electrode of the capacitor C131 and the gate of the n-channel TFT n131. The emitter of the npn-type bipolar transistor T131 is connected to one electrode of the capacitor C132 and the gate of the n-channel TFT n132. The collector of the npn-type bipolar transistor T131 and the collector of the transistor T132 are connected to the positive power voltage VB. It is to be noted that the level shift circuit section has the same construction as that of the conventional level shift circuit shown in FIG. 12.
Reference is made to the operation of the conventional level shift circuit shown in FIG. 13. An input signal IN is capacitively coupled with the capacitor C131 and inputted to the gate of the n-channel TFT n131, while an input signal (/IN) is capacitively coupled with the capacitor C132 and inputted to the gate of the n-channel TFT n132. In this case, due to a voltage from the voltage clamp circuit section, the input signals IN and (/IN), of which the amplitudes are not changed, have their low levels shifted to voltages dropped by the forward voltage from the voltage VBxe2x80x2. That is, even when the threshold voltages of the transistors that constitute the level shift circuit section become high, then the high levels of the input signals IN and (/IN) can be set higher than the respective threshold voltages, allowing the transistors to be correctly turned on and off. Then, the level shift circuit section amplifies the amplitude of the input signal IN similarly to the conventional level shift circuit shown in FIG. 12.
However, the above-mentioned level shift circuit has had the problem that the circuit needs the two input signals of the input signals IN and (/IN) that have a relation of inverted voltage levels. That is, if the driver monolithic type TFT liquid crystal display device shown in FIG. 11 has the aforementioned level shift circuit built-in, then, with regard to the start pulses SPV and SPH, the input control signals are not required to have the relation of inverted voltage levels in terms of driving the shift registers 3 and 4, but the level shift circuit needs two input control signals having the relation of inverted voltage levels. This leads to an increase in the number of external input signals when forming the driver monolithic type TFT liquid crystal display device and consequently leads to an increase in the number of connection terminals for the external signals.
The aforementioned level shift circuit, in which the voltage clamp circuit section is constructed of the npn-type bipolar transistors T131 and T132, has had the problem that it is hard to monolithically form the level shift circuit of polysilicon on the same substrate as that of the drive circuit. That is, the voltage clamp circuit is required to be externally provided, causing an increase in the number of components.
Furthermore, the aforementioned level shift circuit has had the problem that, when the threshold voltages of the p-channel TFT""s p131, p132 and p133 and the n-channel TFT""s n131, n132 and n133 constituting the level shift circuit fluctuate, the voltage VB, is required to be adjusted according to the threshold voltages of the transistors. That is, the positive power voltage VB or the resistors R131 and R132 must be adjusted in value according to the threshold voltages of the transistors. In general, the variation in the threshold voltages of the transistors formed of polysilicon is greater than that of the transistors formed of single crystal silicon, and it is very inefficient to adjust the voltage VB every liquid crystal display device when putting mass production into practice.
The present invention has been made to solve the aforementioned problems and provides a level shift circuit and an image display device that operate with one input signal, allow the whole level shift circuit to be monolithically formed of polysilicon on a substrate identical to that of a drive circuit and are not required to have the power voltage and resistance values adjusted for each liquid crystal display device.
In order to solve the above problems, there is provided a level shift circuit having a capacitance means provided for an input section, a bias voltage setting means for setting a DC voltage level of an input signal capacitively coupled with the capacitance means and an amplifying means for amplifying the amplitude of the input signal of which the DC voltage level is set,
the bias voltage setting means being constituted by providing a voltage dividing means between a positive power voltage and a negative power voltage and the amplifying means having one input signal line.
Also, there is provided an image display device employing a level shift circuit provided with a capacitance means provided for an input section, a bias voltage setting means for setting a DC voltage level of an input signal capacitively coupled with the capacitance means and an amplifying means for amplifying the amplitude of the input signal,
the bias voltage setting means being constituted by providing a voltage dividing means between a positive power voltage and a negative power voltage, and the amplifying means having one input signal line.
According to the above level shift circuit and image display device, the bias voltage setting means is constituted by providing the voltage dividing means between the positive power voltage and the negative power voltage. Therefore, the bias voltage setting means can be provided by a simple circuit construction, and the DC voltage level of the input signal can be easily shifted into the range of the operating point of the amplifying means. The input terminal of the amplifying means is constructed of one terminal. Therefore, the level shift circuit is allowed to have a reduced number of input signal lines, and the amplifying means can be provided by a simple circuit construction.
In one embodiment of the present invention, the amplifying means is a CMOS inverter circuit.
According to the above embodiment, the amplifying means is the CMOS inverter circuit. With this arrangement, the amplifying means can be provided by a simple structure employing the p-channel transistor and the n-channel transistor.
In one embodiment of the present invention, a p-channel transistor and an n-channel transistor are employed as the voltage dividing means.
According to the above embodiment, the p-channel transistor and the n-channel transistor are employed as the voltage dividing means. Therefore, the DC voltage level of the input signal can be easily set by the ON-state resistance ratio of the transistors. The level shift circuit can be entirely formed of polysilicon, which has a greater threshold voltage variation than single crystal silicon, on an identical substrate. That is, a driver monolithic type image display device including a level shift circuit can be provided.
In one embodiment of the present invention, capacitors are employed as the voltage dividing means.
According to the above embodiment, the capacitors are employed as the voltage dividing means. Therefore, the DC voltage level of the input signal can be easily set by the areal ratio of the capacitors. The capacitors can also be easily formed on the polysilicon, and therefore, the level shift circuit can be entirely formed on an identical substrate. That is, a driver monolithic type image display device including the level shift circuit can be provided.
In one embodiment of the present invention, resistors are employed as the voltage dividing means.
According to the above embodiment, the resistors are employed as the voltage dividing means. Therefore, the DC voltage level of the input signal can be easily set by the resistance ratio, and the level shift circuit can be entirely formed on an identical substrate. That is, a driver monolithic type image display device including the level shift circuit can be provided.
In one embodiment of the present invention, the bias voltage setting means is constructed so that a source of the p-channel transistor and a gate of the n-channel transistor are connected to the positive power voltage, a gate of the p-channel transistor and a source of the n-channel transistor are connected to the negative power voltage, and a drain of the p-channel transistor and a drain of the n-channel transistor are connected to an input terminal of the amplifying means.
According to the above embodiment, the bias voltage setting means is constructed so that the source of the p-channel transistor and the gate of the n-channel transistor are connected to the positive power voltage, the gate of the p-channel transistor and the source of the n-channel transistor are connected to the negative power voltage, and the drain of the p-channel transistor and the drain of the n-channel transistor are connected to the input terminal of the amplifying means. With this arrangement, even if the threshold voltages of the transistors constituting the level shift circuit fluctuate to shift the operating point of the amplifying means, then the DC voltage level of the input signal can be automatically set in response to the shift.
In one embodiment of the present invention, the bias voltage setting means is constructed so that a source of a p-channel transistor is connected to the positive power voltage, a source of an n-channel transistor is connected to the negative power voltage, and a gate and a drain of a p-channel transistor and a gate and a drain of an n-channel transistor are connected to an input terminal of the amplifying means.
According to the above embodiment, the bias voltage setting means is constructed so that the source of the p-channel transistor is connected to the positive power voltage, the source of the n-channel transistor is connected to the negative power voltage, and the gate and the drain of the p-channel transistor and the gate and the drain of the n-channel transistor are connected to the input terminal of the amplifying means. With this arrangement, even if the threshold voltages of the transistors constituting the level shift circuit fluctuate to shift the operating point of the amplifying means, then the DC voltage level of the input signal can be easily set.
In one embodiment of the present invention, the voltage dividing means is constructed of a plurality of p-channel transistors and a plurality of n-channel transistors.
According to the above embodiment, the voltage dividing means is constructed of the plurality of p-channel transistors and the plurality of n-channel transistors. With this arrangement, stress exerted by the electric fields applied across the source and drain of each transistor can be reduced. The DC voltage level of the input signal can be determined by the number of transistors, and this allows the degree of freedom of setting to be increased.
In one embodiment of the present invention, a. level shift circuit further comprises a voltage clamping means for clamping the DC voltage level set by the bias voltage setting means.
According to the above embodiment, the level shift circuit and the image display device of the present invention are provided with the voltage clamping means for clamping the DC voltage level set by the bias voltage setting means. With this arrangement, the waveform distortion of the input signal can be prevented regardless of the frequency of the input signal, the transistors constituting the bias voltage setting means and the capacitance means provided for the input section. This also allows the degree of freedom of setting to be increased.
In one embodiment of the present invention, a level shift circuit further comprises a means for compensating for a voltage drop when the DC voltage level set by the bias voltage setting means are clamped by the voltage clamping means.
According to the above embodiment, the level shift circuit of the present invention is provided with the means for compensating for the voltage drop when the DC voltage level set by the bias voltage setting means is clamped by the voltage clamping means. With this arrangement, the DC voltage level of the input signal can be easily set by the bias voltage setting means.